Model to validate the application of MultiAnd block
Validation test for the block AixLib.Controls.OBC.CDL.Logical.MultiAnd.
The input signals are configured as follows:
- input u1 has a period of 1 s and a
width of 0.5 s.
- input u2 has a period of 2 s and a
width of 0.5 s.
- input u3 has a period of 3 s and a
width of 0.5 s.
- input u4 has a period of 4 s and a
width of 0.5 s.
- input u5 has a period of 5 s and a
width of 0.5 s.
- June 28, 2017, by Jianjun Hu:
First implementation.
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.AixLib.Controls.OBC.CDL.Logical.Validation.MultiAnd