.BondLib.Electrical.Analog.Spice.Jp

Spice-style p-channel JFET

Information

The Spice-style p-channel JFET model contains an internal p-channel JFET together with the three external resistances.

The heating port may remain unconnected, in which case the device is being simulated at a constant temperature of Tnom. 

Parameters:

 Level:   JFET modeling level (default value = 1)
            Level=1: Shichman-Hodges (Si) JFET model
            Level=2: Improved Shichman-Hodges (Si) JFET model [1]
            Level=3: Statz-Curtice (GaAs) MESFET model [2,3]

 Area:    Relative area occupied by the diode (default value = 1) Levels 1-3


Basic Electrical Parameters:

 VT0:     Threshold voltage at reference temperature (default value = 0 Volt) Levels 1-3
            VT0 < 0 for enhancement JFET
            VT0 > 0 for depletion JFET

 LAMBDA:  Channel length modulation (default value = 0 1/Volt) Levels 1-3

 BETA:    Transconductance parameter at reference temperature (default value = 0 Amp/Volt2) Levels 1-3

 N:       Current emission coefficient (default value = 1) Levels 1-3

 IS:      Transport saturation current (default value = 1e-14 Amp) Levels 1-3

 PB:      Built-in potential at reference temperature (default value = 0.8 Volt) Levels 1-3


Parasitic Resistor Parameters:

 RS:      Source resistance (default value = 0 Ohm) Levels 1-3

 RD:      Drain resistance (default value = 0 Ohm) Levels 1-3

 RG:      Gate resistance (default value = 0 Ohm) Levels 1-3


Junction Capacitance Parameters:

 CGS:     Zero-bias gate-source depletion capacitance at reference temperature (default value = 0.5e-12 F) Levels 1-3

 CGD:     Zero-bias gate-drain depletion capacitance at reference temperature (default value = 0.5e-12 F) Levels 1-3

 M:       Junction grading coefficient Levels 1-3
            default value = 0.33 for Levels=1,2 (Si)
            default value = 0.5  for Level=3 (GaAs)

 FC:      Forward-bias depletion capacitance coefficient (default value = 0.5) Levels 1,2


Transit Time Parameters:

 TT:      Ideal transit time (default value = 5e-9 sec) Levels 1,2


Temperature Compensation Parameters:

 Tnom:    Reference temperature (default value = 300.15 K) Levels 1-3

 XTI:     Saturation current temperature exponent Levels 1-3
            default value = 3 for Levels=1,2 (Si)
            default value = 2 for Level=3 (GaAs)

 BEX:     Mobility temperature exponent (default value = 0) Levels 1-3

 EG:      Energy gap for temperature effect on saturation current at 0 K Levels 1-3
            default value = 1.11 Volt for Levels=1,2 (Si)
            default value = 0.73 Volt for Level=3 (GaAs)

 TCV:     Linear temperature coefficient of threshold voltage (default value = 0 Volt/K) Levels 1-3

 TRS:     Linear temperature coefficient of source resistance (default value = 0 1/K) Levels 1-3

 TRD:     Linear temperature coefficient of drain resistance (default value = 0 1/K) Levels 1-3

 TRG:     Linear temperature coefficient of gate resistance (default value = 0 1/K) Levels 1-3


Level=2 Electrical Parameters:

 LAM1:    Channel length modulation gate voltage parameter (default value = 0 1/Volt) Level 2


Level=3 Electrical Parameters:

 ALPHA:   Hyperbolic tangient fitting parameter (default value = 1) Level 3

 B:       Measure of doping profile (default value = 0 1/Volt) Level 3

 DELTA:   Voltage range for transition (default value = 0.2 Volt) Level 3

 VMAX:    Limit voltage for carrier velocity saturation (default value = 0.5 Volt) Level 3


Numerical Parameters:

 EMin:    if x < EMin, the exp(x) function is linearized (default value = -100) Levels 1-3

 EMax:    if x > EMax, the exp(x) function is linearized (default value = 40) Levels 1-3

 GminDC:  Leakage conductance (default value = 1e-15 Mho) Levels 1-3


Compiler Parameters:

 enforceStates:  State selector (default value = true) Levels 1-3
                   enforceStates = true:   Use (external) capacitive voltages as state variables
                   enforceStates = false:  Use (internal) bond graph efforts as state variables

References:

  1. Massobrio, G. and P. Antognetti (1993), Semiconductor Device Modeling with Spice, 2nd edition, McGraw Hill, New York, p.153.
  2. Massobrio, G. and P. Antognetti (1993), Semiconductor Device Modeling with Spice, 2nd edition, McGraw Hill, New York, p.382.
  3. Statz, H., P. Newman, I.W. Smith, R.A. Pucel, and H.A. Hans (1987), "GaAs FET Device and Circuit Simulation in Spice," IEEE Trans. Electron Devices, 34(2), pp. 160-169.
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