The nand gate is a basic CMOS building block. It consists of four CMOS transistors.
The output voltage Nand.y.v is low if and only if the two input voltages at Nand.x1.v and Nand.x2.v
are both high. In this way the nand functionality is realized.
The simulation end time should be set to 1e-7. Please plot the input voltages Nand.x1.v,
d Nand.x2.v, and the output voltage Nand.y.v.
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Reference:
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Tietze, U.; Schenk, Ch.: Halbleiter-Schaltungstechnik. Springer-Verlag Berlin Heidelberg NewYork 1980, p. 157
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Main Authors:
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Christoph Clauß
<clauss@eas.iis.fhg.de>
André Schneider
<schneider@eas.iis.fhg.de>
Fraunhofer Institute for Integrated Circuits
Design Automation Department
Zeunerstraße 38
D-01069 Dresden
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Copyright:
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Copyright © 1998-2002, Modelica Association and Fraunhofer-Gesellschaft.
The Modelica package is free software; it can be redistributed and/or modified
under the terms of the Modelica license, see the license conditions
and the accompanying disclaimer in the documentation of package
Modelica in file "Modelica/package.mo".
Contents
| Name | Description |
|---|
| Nand | CMOS NAND Gate |
| TestNand | Test circuit to evaluate performance of NAND gate |
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