Example that demonstrates the use of the signal ranker model.
The figure below shows the input and output signals of the block.
Note that
sigRan.y[1] ≥ sigRan.y[2] ≥ sigRan.y[3].
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October 15, 2021, by Michael Wetter:
Moved start time of sine input signal to avoid simultaneous state event and time event.
This is for
IBPSA, #1534.
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November 21, 2011, by Michael Wetter:
Added documentation.
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