modelPLL

Phase-Locked Loop

Information

The PLL calculates the frequency of the grid voltage by synchronizing the internal phase angle with measured voltage phasor. q-component of internal voltage phasor is therefore controlled to be zero.

Following relationship is used to calculate internal voltage phasor q-component:

   uqPu = uiPu * cos(phi) - urPu * sin(phi);

If uqPu is zero, the internal phasor is locked with the measured phasor and rotates with the same frequency.

Parameters

TypeNameDefaultDescription
Types.PerUnitKiPLL integrator gain
Types.PerUnitKpPLL proportional gain
Types.PerUnitOmegaMaxPuUpper frequency limit in pu (base OmegaNom)
Types.PerUnitOmegaMinPuLower frequency limit in pu (base OmegaNom)
Types.ComplexVoltagePuu0PuStart value of complex voltage at PCC in pu (base UNom)

Connectors

TypeNameDefaultDescription
Modelica.Blocks.Interfaces.RealInputomegaRefPuReference frequency of the system in pu (base OmegaNom)
Modelica.ComplexBlocks.Interfaces.ComplexInputuPuComplex voltage at PCC in pu (base UNom)
Modelica.Blocks.Interfaces.RealOutputomegaPLLPuMeasured frequency in pu (base OmegaNom)
Modelica.Blocks.Interfaces.RealOutputphiVoltage phase at PCC in rad

Components

TypeNameDefaultDescription
Modelica.Blocks.Continuous.Integratorintegrator
Modelica.Blocks.Math.Addadd2
Modelica.Blocks.Sources.RealExpressionrealExpression
Modelica.Blocks.Continuous.LimIntegratorlimIntegrator
Modelica.Blocks.Math.Addadd1
Modelica.Blocks.Math.Gaingain