.IDEAS.Controls.OBC.CDL.Logical.Sources.SampleTrigger

Information

The Boolean output y is a trigger signal that is only true at sample times (defined by parameter period) and is otherwise false.

The trigger signal is generated an infinite number of times, and aligned with time=delay.

Revisions

• December 03, 2020, by Milica Grahovac:
  Renamed delay parameter to shift.
  This is for Buildings, issue 2282.
• November 12, 2020, by Michael Wetter:
  Reformulated to remove dependency to Modelica.Units.SI.
  This is for Buildings, issue 2243.
• October 19, 2020, by Michael Wetter:
  Refactored implementation.
  This is for Buildings, issue 2170.
• March 23, 2017, by Jianjun Hu:
  First implementation, based on the implementation of the Modelica Standard Library.