Validation test for the block IDEAS.Controls.OBC.CDL.Routing.RealExtractSignal.
The instance extSig has the input vector with
dimension of 4 and the extracting vector is [1, 2, 5].
Thus the output vectors is [u[1], u[2], u[5]].
The instance extSig1 has the input vector with
dimension of 4 and the extracting vector is [1, 2, 5, 3, 4,
2]. Thus the output vectors is [u[1], u[2], u[5],
u[3], u[4], u[2]].
Note that when the extracting vector extract has
any element with the value that is out of range [1,
nin], e.g. [1, 4] for instance in
extSig. It will issue error and the model will not
translate.