Description
The timer is active after a rising edge of the set signal ( S ).
The output ( Q ) of the timer rises up PV seconds after the Set ( S )
becomes true.
If the Set signal become false while counting, the timer does not stop.
If the Reset signal ( R ) becomes true, the output remains false and the timer stops.
Images show:
- Set S and Reset R signals,
- Output Q,
- and the remaining time tr
- First release of the Industrial Control Systems: April-May 2012
- List of revisions:
- 11 May 2012 (author: Marco Bonvini)
- Main Authors:
- Marco Bonvini; <bonvini@elet.polimi.it>
- Alberto Leva <leva@elet.polimi.it>
- Politecnico di Milano
- Dipartimento di Elettronica e Informazione
- Via Ponzio 34/5
- 20133 Milano - ITALIA -
- Copyright:
- Copyright © 2010-2012, Marco Bonvini and Alberto Leva.
- The IndustrialControlSystems package is free software; it can be redistributed and/or modified under the terms of the Modelica license, see the license conditions and the accompanying disclaimer in the documentation of package Modelica in file "Modelica/package.mo".
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.IndustrialControlSystems.Logical.Timers.Timer_OffDelay_Redge