typeChannelKind
Kind of a channel of the logic analyser probe
Information
Kind of a channel of Peripherals.Analyzers.LogicAnalyzer. Every channel that is not Off is recorded (VCD file) and drawn in the timing diagram of the text file; a decoded channel (Uart, I2cSda, SyncData) also shows its bits and bytes under its waveform, and its bytes in the hexadecimal section.
A clock line (SCL of an I2C bus, PD_SCK of an HX711, SCK of an SPI link) is a plain Logic channel: it is the data channel that names its clock channel (clockChannel), so that several buses can share the probe without ambiguity.
Literals
| Name | Description |
|---|---|
| Off | Not recorded (no threshold-crossing function) |
| Logic | Logic level only (also the kind of a clock channel) |
| Uart | Serial link (UART) decoded with the format of the channel |
| I2cSda | SDA line of an I2C bus, its SCL line on clockChannel |
| SyncData | Data of a synchronous serial link (HX711, simplified SPI), its clock on clockChannel |