.Modelica.Blocks.Logical

Information

This package provides blocks with Boolean input and output signals to describe logical networks. A typical example for a logical network built with package Logical is shown in the next figure:

LogicalNetwork1.png

The actual value of Boolean input and/or output signals is displayed in the respective block icon as "circle", where "white" color means value false and "green" color means value true. These values are visualized in a diagram animation.

Contents

NameDescription
 AndLogical 'and': y = u1 and u2
 OrLogical 'or': y = u1 or u2
 XorLogical 'xor': y = u1 xor u2
 NorLogical 'nor': y = not (u1 or u2)
 NandLogical 'nand': y = not (u1 and u2)
 NotLogical 'not': y = not u
 PreBreaks algebraic loops by an infinitesimal small time delay (y = pre(u): event iteration continues until u = pre(u))
 EdgeOutput y is true, if the input u has a rising edge (y = edge(u))
 FallingEdgeOutput y is true, if the input u has a falling edge (y = edge(not u))
 ChangeOutput y is true, if the input u has a rising or falling edge (y = change(u))
 GreaterThresholdOutput y is true, if input u is greater than threshold
 GreaterEqualThresholdOutput y is true, if input u is greater or equal than threshold
 LessThresholdOutput y is true, if input u is less than threshold
 LessEqualThresholdOutput y is true, if input u is less or equal than threshold
 GreaterOutput y is true, if input u1 is greater than input u2
 GreaterEqualOutput y is true, if input u1 is greater or equal than input u2
 LessOutput y is true, if input u1 is less than input u2
 LessEqualOutput y is true, if input u1 is less or equal than input u2
 ZeroCrossingTrigger zero crossing of input u
 LogicalSwitchLogical Switch
 SwitchSwitch between two Real signals
 HysteresisTransform Real to Boolean signal with Hysteresis
 OnOffControllerOn-off controller
 TriggeredTrapezoidTriggered trapezoid generator
 TimerTimer measuring the time from the time instant where the Boolean input became true
 LogicalDelayDelay boolean signal
 RSFlipFlopA basic RS Flip Flop
 TerminateSimulationTerminate simulation if condition is fulfilled

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