This library contains packages for digital electrical components. Both, type system and models are based on the VHDL standard (IEEE Std 1076-1987 VHDL, IEEE Std 1076-1993 VHDL, IEEE Std 1164 Multivalue Logic System):
The logic values are coded by integer values. The following code table is necessary for both setting of input and interpreting the output values.
Code Table:
| Logic value | Integer code | Meaning |
| 'U' | 1 | Uninitialized |
| 'X' | 2 | Forcing Unknown |
| '0' | 3 | Forcing 0 |
| '1' | 4 | Forcing 1 |
| 'Z' | 5 | High Impedance |
| 'W' | 6 | Weak Unknown |
| 'L' | 7 | Weak 0 |
| 'H' | 8 | Weak 1 |
| '-' | 9 | Do not care |
The library will be developed in two main steps. The first step contains the basic components and the gates. In the next step the more complicated devices will be added. Currently the first step of the library is implemented and released for public use.
Copyright © 1998-2020, Modelica Association and contributors
| Name | Description |
|---|---|
| UsersGuide | User's Guide |
| Examples | Examples that demonstrate the usage of the Digital electrical components |
| Interfaces | Basic definitions |
| Tables | Truth tables for all components of package Digital |
| Delay | Delay blocks |
| Basic | Basic logic blocks without delays |
| Gates | Logic gates including delays |
| Sources | Time-dependent digital signal sources |
| Converters | Converters between 2-,3-,4- and 9-valued logic |
| Registers | Registers with N-bit input data and output data |
| Tristates | Transfergates, Buffers, Inverters, and WiredX |
| Memories | |
| Multiplexers |