blockHoldWithDAeffects
Extends from Clocked.RealSignals.Interfaces.PartialSISOHold (Basic block used for zero order hold of Real signals).
Information
This block is similar to the Hold block. The only difference is that simulated real-world effects are applied on the clocked input signal u before transforming the signal to a continuous-time signal with a zero-order hold. In particular:
- The output is delayed by a fraction of the clock period, if parameter computationalDelay = true. The delay is defined by shiftCounter/resolution*interval(), where shiftCounter and resolution are Integer parameters and interval() is the time duration from the previous to the current clock tick. The maximal possible computational delay is one clock duration, and therefore there is the restriction that shiftCounter ≤ resolution.
- The output is limited, if parameter limited = true.
- The output is value discretized in the form of an Digital-Analog converter with a definable number of bits, if parameters limited = true, and quantized = true.
Example
The following example samples a sine signal with an amplitude of 2.0 with a periodic clock of 20 ms period and delays it for 2 sample periods. The resulting signal is hold with the HoldWithDAeffects block. As a result, the clock of hold.u starts ticking at 40 ms. The output hold.y of the block is a continuous-time signal that is present from the start of the simulation. Before the first tick of the clock of hold.u, it is set to 0.5 (= the value of parameter hold.y_start). Additionally, the following effects are added to the hold block:
- The output is limited to +/- 1.9.
- A computational delay of half of a sample period (= 1/2*20 ms = 10 ms)
is defined.
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|
| model | simulation result |
Due to the limitation of the output signal, the values of hold.u ≥ 1.9
are limited to 1.9.
If the hold output is delayed by one sample period, then the previous(…) value of the
input is output, and the first tick is delayed by one sample period,
as shown by the
modified example
from above:
 |
 |
|
| model | simulation result |
Note, the computational delay of one sample period is defined
by shiftCounter=1, resolution=1, as shown in the icon of the
hold block.
Parameters
| Type | Name | Default | Description |
|---|---|---|---|
| Real | y_start (from PartialSISOHold) | 0.0 | Value of output y before the first tick of the clock associated to input u |
| Computational delay in seconds = interval() * shiftCounter/resolution | |||
| Boolean | computationalDelay | false | =true, if a computational delay should be imposed |
| Integer | shiftCounter | 0 | (min=0, max=resolution), computational delay = interval()*shiftCounter/resolution |
| Integer | resolution | 1 | Time quantization resolution of sample interval |
| Limiting and quantization | |||
| Boolean | limited | false | = true, if output is limited |
| Boolean | quantized | false | = true, if output quantization effects included |
| Real | yMax | 1 | Upper limit of output (if limited = true) |
| Real | yMin | -yMax | Lower limit of output (if limited = true) |
| Integer | bits | 8 | Number of bits of quantization (if quantized = true) |
Connectors
| Type | Name | Default | Description |
|---|---|---|---|
| Modelica.Blocks.Interfaces.RealInput | u (from PartialSISOHold) | Connector of clocked, Real input signal | |
| Modelica.Blocks.Interfaces.RealOutput | y (from PartialSISOHold) | Connector of continuous-time, Real output signal |
Components
| Type | Name | Default | Description |
|---|---|---|---|
| Clocked.RealSignals.Sampler.Utilities.Internal.Limiter | limiter | ||
| Clocked.RealSignals.Sampler.Utilities.Internal.Quantization | quantization | ||
| Clocked.RealSignals.Sampler.Utilities.Internal.ComputationalDelay | compDelay | ||
| Hold | hold1 |