modelDLATROM
Level sensitive Read Only Memory
Extends from Interfaces.MemoryBase (Base model for memory elements).
Information
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table for high active read enable RE:
| RE | Addr | DataOut |
| 0 | * | Z over all |
| 1 | no X in Addr | DataOut=m(Addr) |
| 1 | X in Addr | X over all |
| X | * | X over all |
* = do not care 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' or L.'U' Z = L.'Z'
Parameters
| Type | Name | Default | Description |
|---|---|---|---|
| SI.Time | tHL (from MemoryBase) | 0 | High->Low delay |
| SI.Time | tLH (from MemoryBase) | 0 | Low->High delay |
| S | strength (from MemoryBase) | S.'S_X01' | Output strength |
| Integer | n_addr (from MemoryBase) | 2 | Addr width |
| Integer | n_data (from MemoryBase) | 2 | Data width |
| Table data definition | |||
| String | fileName (from MemoryBase) | Modelica.Utilities.Files.loadResource("modelica://Modelica/Resources/Data/Electrical/Digital/Memory_Matrix.txt") | File where matrix for memory is stored |
Connectors
| Type | Name | Default | Description |
|---|---|---|---|
| DigitalInput | RE (from MemoryBase) | Read enable | |
| DigitalInput[n_addr] | addr (from MemoryBase) | Address | |
| DigitalOutput[n_data] | dataOut (from MemoryBase) | Data output |
Revisions
- October 19, 2010
- created by Ulrich Donath