modelMUX2x1
A two inputs MULTIPLEXER for multiple value logic (2 data inputs, 1 select input, 1 output)
Information
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
and for Multiplexer table http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd
Truth Table
DataIn |
Select |
DataOut |
* |
0 |
Input0 |
* |
1 |
Input1 |
Inputs equal |
U |
Input |
Inputs not equal |
U |
U |
U in Input |
X |
U |
Inputs equal |
X |
Input |
no U in Input and Inputs not equal |
X |
X |
* = don't care 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' U = L.'U'
Parameters
| Type | Name | Default | Description |
|---|---|---|---|
| SI.Time | tHL | 0 | High->Low delay |
| SI.Time | tLH | 0 | Low->High delay |
| D.Interfaces.Strength | strength | S.'S_X01' | Output strength |
Connectors
| Type | Name | Default | Description |
|---|---|---|---|
| D.Interfaces.DigitalInput | in1 | Data input 1 | |
| D.Interfaces.DigitalInput | in0 | Data input 0 | |
| D.Interfaces.DigitalInput | sel | Select input | |
| D.Interfaces.DigitalOutput | out | Output |
Revisions
- January 24, 2011
- created by Christian Günther