modelDFFREGSRH
Edge triggered register bank with high active set and reset
Information
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
| DataIn | Clock | Reset | Set | DataOut |
| * | * | * | U | U |
| * | * | U | * | U |
| * | * | * | 1 | 1 |
| * | * | 1 | 0 | 0 |
| * | * | 1 | X | X |
| * | * | X | X | X or U |
| * | * | 0 | X | X or U or 1 or NC |
| * | * | X | 0 | X or U or 0 or NC |
| * | X-Trns | 0 | 0 | X or U or NC |
| * | 1-Trns | 0 | 0 | DataIn |
| * | 0-Trns | 0 | 0 | NC |
* = do not care ~ = not equal U = L.'U' 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' NC = no change Clock transition definitions: 1-Trns: 0 -> 1 0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U X-Trns: 0 -> X|U or X|U -> 1
Parameters
| Type | Name | Default | Description |
|---|---|---|---|
| SI.Time | tHL | 0 | High->Low delay |
| SI.Time | tLH | 0 | Low->High delay |
| D.Interfaces.Strength | strength | S.'S_X01' | Output strength |
| Integer | n | 1 | Data width |
Connectors
| Type | Name | Default | Description |
|---|---|---|---|
| D.Interfaces.DigitalInput | set | ||
| D.Interfaces.DigitalInput | reset | ||
| D.Interfaces.DigitalInput | clock | ||
| D.Interfaces.DigitalInput[n] | dataIn | ||
| D.Interfaces.DigitalOutput[n] | dataOut |
Revisions
- September 11, 2009 created by Ulrich Donath