modelDFFSR

Edge triggered register bank with set and reset
Diagram of DFFSROpen the diagram
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Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active set and reset

DataIn Clock Reset Set DataOut Map
* * * U U 1
* * U * U 1
* * * 1 1 2
* * 1 0 0 3
* * 1 X X 6
* * X X X or U 4
* * 0 X X or U or 1 or NC 5
* * X 0 X or U or 0 or NC 7
* X-Trns 0 0 X or U or NC 8
* 1-Trns 0 0 DataIn 8
* 0-Trns 0 0 NC 8

Truth Table for low active set and reset

DataIn Clock Reset Set DataOut Map
* * * U U 1
* * U * U 1
* * * 0 1 2
* * 0 1 0 3
* * 0 X X 6
* * X X X or U 4
* * 1 X X or U or 1 or NC 5
* * X 1 X or U or 0 or NC 7
* X-Trns 1 1 X or U or NC 8
* 1-Trns 1 1 DataIn 8
* 0-Trns 1 1 NC 8 
  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Parameters

TypeNameDefaultDescription
Integer[L,L]ResetSetMap[1, 1, 1, 1, 1, 1, 1, 1, 1; 1, 4, 7, 2, 4, 4, 7, 2, 4; 1, 5, 8, 2, 5, 5, 8, 2, 5; 1, 6, 3, 2, 6, 6, 3, 2, 6; 1, 4, 7, 2, 4, 4, 7, 2, 4; 1, 4, 7, 2, 4, 4, 7, 2, 4; 1, 5, 8, 2, 5, 5, 8, 2, 5; 1, 6, 3, 2, 6, 6, 3, 2, 6; 1, 4, 7, 2, 4, 4, 7, 2, 4]Function selection by [reset, set] reading
D.Interfaces.StrengthstrengthS.'S_X01'Output strength
Integern1Data width

Connectors

TypeNameDefaultDescription
D.Interfaces.DigitalInputset
D.Interfaces.DigitalInputreset
D.Interfaces.DigitalInputclock
D.Interfaces.DigitalInput[n]dataIn
D.Interfaces.DigitalOutput[n]dataOut

Revisions

  • September 11, 2009 created by Ulrich Donath