modelDLATREGSRL
Level sensitive register bank with set and reset, active low
Extends from Digital.Registers.DLATREGSRH (Level sensitive register bank with set and reset, active high).
Information
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
| DataIn | Enable | Reset | Set | DataOut |
| * | * | * | U | U |
| * | * | U | ~0 | U |
| * | * | * | 0 | 1 |
| * | * | 0 | 1 | 0 |
| * | * | 0 | X | X |
| * | U | ~0 | ~0 | U |
| * | ~U | X | X | X or U |
| * | ~U | 1 | X | X or U or 1 or NC |
| * | ~U | X | 1 | X or U or 0 or NC |
| * | X | 1 | 1 | X or U or NC |
| * | 1 | 1 | 1 | DataIn |
| * | 0 | 1 | 1 | NC |
* = do not care ~ = not equal U = L.'U' 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' NC = no change
Parameters
| Type | Name | Default | Description |
|---|---|---|---|
| SI.Time | tHL (from DLATREGSRH) | 0 | High->Low delay |
| SI.Time | tLH (from DLATREGSRH) | 0 | Low->High delay |
| D.Interfaces.Strength | strength (from DLATREGSRH) | S.'S_X01' | Output strength |
| Integer | n (from DLATREGSRH) | 1 | Data width |
Connectors
| Type | Name | Default | Description |
|---|---|---|---|
| D.Interfaces.DigitalInput | set (from DLATREGSRH) | ||
| D.Interfaces.DigitalInput | reset (from DLATREGSRH) | ||
| D.Interfaces.DigitalInput | enable (from DLATREGSRH) | ||
| D.Interfaces.DigitalInput[n] | dataIn (from DLATREGSRH) | ||
| D.Interfaces.DigitalOutput[n] | dataOut (from DLATREGSRH) |
Components
| Type | Name | Default | Description |
|---|---|---|---|
| D.Delay.InertialDelaySensitiveVector | delay (from DLATREGSRH) | ||
| D.Registers.DLATSR | dLATSR (from DLATREGSRH) |
Revisions
- September 11, 2009 created by Ulrich Donath