modelPRXFERGATE
Transfergate with enable active low. Output strength reduced.
Information
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
| DataIn | Enable | DataOut |
| * | U | U |
| * | X | UW |
| * | 0 | DataIn, Strength Reduced |
| * | 1 | Z |
| * | Z | UW |
| * | W | UW |
| * | L | DataIn, Strength Reduced |
| * | H | Z |
| * | - | UW |
UW: if dataIn == U then U else W Strength Reduced: 0 -> L, 1 -> H, X -> W
Parameters
| Type | Name | Default | Description |
|---|---|---|---|
| SI.Time | tHL | 0 | High->Low delay |
| SI.Time | tLH | 0 | Low->High delay |
Connectors
| Type | Name | Default | Description |
|---|---|---|---|
| D.Interfaces.DigitalInput | enable | ||
| D.Interfaces.DigitalInput | x | ||
| D.Interfaces.DigitalOutput | y |
Revisions
- January 15, 2010 created by Ulrich Donath