.Modelica_Synchronous.WorkInProgress.Tests .Modelica_Synchronous.WorkInProgress.Tests| Name | Description |
|---|---|
 TestFIR_1 | |
 TestFIR | |
 TestFIR_Step | |
 TestFIR_Step2 | |
 TestFIR_Step2b | |
 TestInterpolator | |
 TestUnitDelay | |
 TestTransferFunction | |
 TestStateSpace | |
 TestRealSampler | |
 TestShiftSample | |
 TestClockedRealToTrigger | |
 TestClockedBooleanToTrigger | |
 TestClockedIntegerToTrigger | |
 TestBackSample | |
 TestClockedRealToSquare | |
 TestIntegerSamplerAndHolds | |
 TestBooleanSamplerAndHolds | |
 TestReplaceableSamplerHold | Using partial sample and hold blocks to allow redeclaration of blocks to simulated communication blocks |
 TestSimulatedADC | |
 TestCommunicationDelay | |
 TestEventClockWithIntegrator | |
 TestExactClockWithIntegrator | |
 TestSuperSampleClock | |
 TriggeredBooleanSampler | Triggered sampling of continuous signals |
 TriggeredIntegerSampler | Triggered sampling of continuous signals |
 TestExactClockWithSolver | |
 Effects | Examples demonstrating specific effects |