.OpenRESV.RES_Model_vs_PHIL_Inverter_Examples.VoltageRideThrough

Example of Voltage Ride Through for Terminal Voltage Dip

Information

The examples found in this package are meant for testing, validating, and analysing the simulation output the WECC-based PV model against experimental data from the ALSETLab Volta Facility. The examples tries to recreate the inverter's response to a terminal voltage variance by replaying the experimental voltage variation and analyzing the the output response of the inverter model against the experimental data. In this experiment, the voltage ride-through add-on module is tested and validated against real world inverter data.

Contents

Name Description
 CircuitBreakerLogic

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