.ScalableTestSuite.Electrical.TransmissionLine.Verification.TransmissionLineCheck

Verification of the transmission line circuits by using time delay

Information

In this model, the verification of the TransmissionLineModelica and the TransmissionLineEquations are performed.The formula of the time delay is used for the verification of the implemented transmission line circuit models to check whether the time delay of the models satisfies the theoretical one. Time delay between the ends of a transmission line can be calculated as follows:

Therefore, using the time delay formula, input voltages of the both models are delayed by the theoretical time delay. Moreover, it is checked whether the output voltages of the transmission line circuit models are matching with the delayed input voltages.

The parameters for the TransmissionLineCheck are:

Parameters	Comment
N	number of segments
L	length of the transmission line
res	resistance per meter
cap	capacitance per meter
ind	inductance per meter
RL	load resistance
w	cut-off frequency
TD	time delay of the transmission line
v	velocity of the signal

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