| Name | Description |
|---|---|
| PwCapacitorBankWithModification | Capacitor Bank with Bank modification at time t1. 2014/03/10 |
| PwCapacitorBank | Capacitor Bank with Bank.2013 |
| PwShuntC | Shunt capacitor |
| PwShuntR | Shunt inductor |
| PwShunt | Thyristor controlled Shunt reactor/capacitor |
| PSSE | |
| Simulink | |
| PwShuntB | |
| CSVGN1 | STATC SHUNT COMPENSATOR MODEL |
Copyright 2015-2016 RTE (France), SmarTS Lab (Sweden), AIA (Spain) and DTU (Denmark)
The authors can be contacted by email: info@itesla-ipsl.org
This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0.
If a copy of the MPL was not distributed with this file, You can obtain one at http://mozilla.org/MPL/2.0.