| Name | Description |
|---|---|
| NegCurLogic | |
| HV_GATE | |
| LV_GATE | |
| Relay | Relay |
| Relay3 | input dependent output |
| Relay4 |
Copyright 2015-2016 RTE (France), SmarTS Lab (Sweden), AIA (Spain) and DTU (Denmark)
The authors can be contacted by email: info@itesla-ipsl.org
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If a copy of the MPL was not distributed with this file, You can obtain one at http://mozilla.org/MPL/2.0.