modelCgb
Spice-style gate capacitance between gate and bulk of MOSFETs
Extends from Interfaces.SpiceTwoPortV (TwoPort interface for Spice-style models).
Information
The Spice-style gate capacitances for MOSFETs are non-linear capacitors that use different formulae to compute the capacitance value in the four different regions: accumulation, depletion, saturation, and the linear region. Different Spice dialects vary in the formulae they use for this purpose. Many Spice dialects actually don't use a formula for the gate capacitances at all, but rather compute the electric charges stored in these regions directly, which is conceptually cleaner. However, that approach is computationally cumbersome, as it leads to an awkward algebraic loop [1]. Thus, we chose to compute the gate capacitances directly, and use a (physically incorrect) approximate non-linear capacitor model. The numerical error should remain small, as the time constants associated with temperature variation are much larger than those associated with electrical phenomena.This particular model uses the space charge formula advocated in [2].
Parameters:
Level: MOSFET modeling level (default value = 3)
Level=0: Static injection model
Level=1: Shichman-Hodges model
Level=2: Grove-Frohman model
Level=3: Empirical model
Level=4: Simplified Grove-Frohman model
Type: Type of MOSFET (default value = 1)
Type = +1: NMOS
Type = -1: PMOS
Tnom: Reference temperature (default value = 300.15 K)
VFB: Flat band voltage at reference temperature (default value = 0 Volt)
KP: Transconductance parameter at reference temperature (default value = 0 Amp/Volt2)
GAMMA: Body-effect parameter (default value = Volt0.5)
PHI: Surface inversion potential at reference temperature (default value = 0 Volt)
COX: Specific capacitance of SiO2 (default value = 0 F/m2)
NFS: Surface fast state density (default value = 0 1/m2)
XJ: Metallurgical junction depth (default value = 0 m)
L: Channel length (default value = 1e-4 m)
W: Channel width (default value = 1e-4 m)
LD: Lateral diffusion (default value = 0 m)
XD: Depletion factor (default value = 0 m/Volt0.5)
XQC: Coefficient of channel charge share (default value = 0)
XQC <= 0.5: Ward-Dutton model of gate capacitance computation
XQC > 0.5: Meyer model of gate capacitance computation
DELTA: Width effect on threshold voltage (default value = 0)
ETA: Static feedback on threshold voltage (default value = 1)
CGB0: Gate-bulk overlap capacitance per meter (default value = 1e-12 F/m)
EG: Energy gap for temperature effect on saturation current (default value = 1.11 Volt)
References:
- Cellier, F.E. (1991), Continuous System Modeling, Springer-Verlag, New York, pp. 224-225.
- Massobrio, G. and P. Antognetti (1993), Semiconductor Device Modeling with Spice, 2nd edition, McGraw Hill, New York, pp.196-197.
Parameters
| Type | Name | Default | Description |
|---|---|---|---|
| Modelica.SIunits.Voltage | u0 (from OnePortV) | 0 | Initial voltage across capacitor |
| Modelica.SIunits.Temperature | Tnom (from SpiceTwoPortV) | 300.15 | Reference temperature |
| Integer | Level | 3 | Level of MOS model (check documentation window for details) |
| Integer | Type | 1 | Type=1 for NMOS; Type=-1 for PMOS |
| Modelica.SIunits.Voltage | VFB | 0 | Flat band voltage at reference temperature |
| Modelica.SIunits.Transconductance | KP | 0 | Transconductance parameter at reference temperature |
| Real | GAMMA | 0 | Body-effect parameter |
| Modelica.SIunits.Voltage | PHI | 0 | Surface inversion potential at reference temperature |
| Real | COX | 0 | Specific capacitance of SiO2 |
| Real | NFS | 0 | Surface fast state density |
| Modelica.SIunits.Length | XJ | 0 | Metallurgical junction depth |
| Modelica.SIunits.Length | L | 1e-4 | Channel length |
| Modelica.SIunits.Length | W | 1e-4 | Channel width |
| Modelica.SIunits.Length | LD | 0 | Lateral diffusion |
| Real | XD | 0 | Depletion factor |
| Real | XQC | 0 | Coefficient of channel charge share |
| Real | DELTA | 0 | Width effect on threshold voltage |
| Real | ETA | 0 | Static feedback on threshold voltage |
| Real | CGB0 | 1e-12 | Gate-bulk overlap capacitance per meter |
| Modelica.SIunits.Voltage | EG | 1.11 | Energy gap for temperature effect on saturation current at 0 K |
| Advanced | |||
| Boolean | enforceStates (from OnePortV) | true | Use electrical variables as states instead of bond graph variables |
Connectors
| Type | Name | Default | Description |
|---|---|---|---|
| Modelica.Electrical.Analog.Interfaces.PositivePin | p (from OnePortV) | Left electrical connector | |
| Modelica.Electrical.Analog.Interfaces.NegativePin | n (from OnePortV) | Right electrical connector | |
| Modelica.Thermal.HeatTransfer.Interfaces.HeatPort_a | heatPort (from SpiceTwoPortV) | may remain unconnected | |
| Modelica.Blocks.Interfaces.RealInput | vds | Drain-source voltage | |
| Modelica.Blocks.Interfaces.RealInput | vbs | Base-source voltage | |
| Modelica.Blocks.Interfaces.RealInput[5] | u | Connector of Real input signals |
Components
| Type | Name | Default | Description |
|---|---|---|---|
| Modelica.SIunits.Voltage | v (from OnePortV) | Voltage drop between the two pins | |
| Modelica.SIunits.Current | i (from OnePortV) | Current flowing from pin p to pin n |