.Buildings.Controls.OBC.CDL.Logical.Latch

Information

Block that generates a true output when the latch input u rises from false to true, provided that the clear input clr is false or also became at the same time false. The output remains true until the clear input clr rises from false to true.

If the clear input clr is true, the output y switches to false (if it was true) and it remains false, regardless of the value of the latch input u.

At initial time, if clr = false, then the output will be y = u. Otherwise it will be y=false (because the clear input clr is true).

Revisions

• October 13, 2020, by Jianjun Hu:
  Removed the parameter pre_y_start, and made the initial output to be equal to latch input when the clear input is false.
  This is for issue 2177.
• March 9, 2020, by Michael Wetter:
  Simplified implementation, and made model work with OpenModelica.
• April 4, 2019, by Jianjun Hu:
  Corrected implementation that causes wrong output at initial stage. This is for issue 1402.
• December 1, 2017, by Michael Wetter:
  Revised documentation.
• March 30, 2017, by Jianjun Hu:
  First implementation.