.Buildings.Controls.OBC.CDL.Logical

Information

Package with blocks for elementary mathematical functions for boolean variables.

Contents

Name	Description
And	Logical 'and': y = u1 and u2
Change	Output y is true, if the input u has a rising or falling edge (y = change(u))
Edge	Output y is true, if the input u has a rising edge (y = edge(u))
FallingEdge	Output y is true, if the input u has a falling edge (y = edge(not u))
Latch	Maintains a true signal until change condition
MultiAnd	Logical MultiAnd, y = u[1] and u[2] and u[3] and ...
MultiOr	Logical MultiOr, y = u[1] or u[2] or u[3] or ...
Nand	Logical 'nand': y = not (u1 and u2)
Nor	Logical 'nor': y = not (u1 or u2)
Not	Logical not
Or	Logical 'or': y = u1 or u2
Pre	Breaks algebraic loops by an infinitesimal small time delay (y = pre(u): event iteration continues until u = pre(u))
Proof	Verify two boolean inputs
Switch	Switch between two boolean signals
Timer	Timer measuring the time from the time instant where the Boolean input became true
TimerAccumulating	Accumulating timer that can be reset
Toggle	Toggles output value whenever its input turns true
TrueDelay	Delay a rising edge of the input, but do not delay a falling edge.
TrueFalseHold	Block that holds an output signal for at least a specified duration
TrueHold	Block that holds a true signal for at least a requested duration
VariablePulse	Generate boolean pulse with the width specified by input
Xor	Logical 'xor': y = u1 xor u2
Sources	Package with blocks that generate source signals
Validation	Collection of models that validate the logical blocks of the CDL

Revisions

• December 22, 2016, by Michael Wetter:
  Firt implementation, based on the blocks from the Modelica Standard Library.