.Buildings.Controls.OBC.CDL.Logical.TrueDelay

Information

Block that delays a signal when it becomes true.

A rising edge of the Boolean input u gives a delayed output. A falling edge of the input is immediately given to the output. If delayOnInit = true, then a true input signal at the start time is also delayed, otherwise the input signal is produced immediately at the output.

Simulation results of a typical example with a delay time of 0.1 second is shown below.

Revisions

• November 12, 2020, by Michael Wetter:
  Reformulated to remove dependency to Modelica.Units.SI.
  This is for issue 2243.
• February 11, 2019, by Milica Grahovac:
  Added boolean input to enable delay of an initial true input.
• January 3, 2017, by Michael Wetter:
  First implementation, based on the implementation of the Modelica Standard Library.