The Limiter block passes its input signal as output signal as long as the input is within the upper and lower limits specified by the two additional inputs limit1 and limit2. If this is not the case, the corresponding limit is passed as output.
For detailed model documentation please consult the html-documentation shipped with ClaRa.
Authorship and Copyright Statement for original (initial) Contribution
Author:
DYNCAP/DYNSTART development team, Copyright © 2011-2023.References:
For references please consult the html-documentation shipped with ClaRa.
Remarks:
This component was developed by ClaRa development team under the 3-clause BSD License.
Acknowledgements:ClaRa originated from the collaborative research projects DYNCAP and DYNSTART. Both research projects were supported by the German Federal Ministry for Economic Affairs and Energy (FKZ 03ET2009 and FKZ 03ET7060).
CLA:
The author(s) have agreed to ClaRa CLA, version 1.0. See https://claralib.com/pdf/CLA.pdf
By agreeing to ClaRa CLA, version 1.0 the author has granted the ClaRa development team a permanent right to use and modify his initial contribution as well as to publish it or its modified versions under the 3-clause BSD License.
The ClaRa development team consists of the following partners:
TLK-Thermo GmbH (Braunschweig, Germany)
XRG Simulation GmbH (Hamburg, Germany).
For revisions please consult the html-documentation shipped with ClaRa.