Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table for high active read enable RE:
| RE | Addr | DataOut |
| 0 | * | Z over all |
| 1 | no X in Addr | DataOut=m(Addr) |
| 1 | X in Addr | X over all |
| X | * | X over all |
* = do not care 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' or L.'U' Z = L.'Z'