Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
and for Multiplexer table http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd
DataIn |
Select |
DataOut |
* |
0 |
Input0 |
* |
1 |
Input1 |
Inputs equal |
U |
Input |
Inputs not equal |
U |
U |
U in Input |
X |
U |
Inputs equal |
X |
Input |
no U in Input and Inputs not equal |
X |
X |
* = don't care 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' U = L.'U'