.Modelica.Electrical.Digital.Tristates.NXFERGATE

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn Enable DataOut
* U U
* X UX
* 0 Z
* 1 DataIn
* Z UX
* W UX
* L Z
* H DataIn
* - UX
UX: if dataIn == U then U else X

Revisions


Generated at 2024-12-04T19:25:49Z by OpenModelicaOpenModelica 1.24.2 using GenerateDoc.mos