modelRAM
Simple RAM test example
Extends from Modelica.Icons.Example (Icon for runnable examples).
Information
This example is a simple and incomplete test of a single DLATRAM component. After simulation until 400 s plot dLATRAM.addr[1], dLATRAM.addr[2], and dLATRAM.dataOUT[1], dLATRAM.dataOut[2]. The address inputs are prescribed with all possible combinations of logic values. It can be checked in which cases of address values the output is 'X' or '0'.