modelDFFREG
Edge triggered register bank with high active reset
Information
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
| DataIn |
Clock |
Reset |
DataOut |
| * | * | U | U |
| * | * | 1 | 0 |
| * | 0-Trns | 0 | NC |
| * | 1-Trns | 0 | DataIn |
| * | X-Trns | 0 | X or U or NC |
| * | * | X | X or U or 0 or NC |
* = do not care
U = L.'U'
0 = L.'0' or L.'L'
1 = L.'1' or L.'H'
X = L.'X' or L.'W' or L.'Z' or L.'-'
NC = no change
Clock transition definitions:
1-Trns: 0 -> 1
0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
X-Trns: 0 -> X|U or X|U -> 1
Revisions
- September 11, 2009 created by Ulrich Donath
