modelDLATREG
Level sensitive register bank with reset active high
Information
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
| DataIn |
Enable |
Reset |
DataOut |
| * | * | U | U |
| * | * | 1 | 0 |
| * | 0 | 0 | NC |
| * | 1 | 0 | DataIn |
| * | X | 0 | X or U or NC |
| * | U | ~1 | U |
| * | ~U | X | X or U or 0 or NC |
* = do not care
~ = not equal
U = L.'U'
0 = L.'0' or L.'L'
1 = L.'1' or L.'H'
X = L.'X' or L.'W' or L.'Z' or L.'-'
NC = no change
Revisions
- September 11, 2009 created by Ulrich Donath
