The output signal (= outPort.signal[1]) is true at the time instant when the input signal (= inPort.signal[1]) becomes zero, provided the enable input (= enable.signal[1]) is true. At all other time instants, the output signal is false. If the input signal is zero at a time instant when the enable input changes its value, then the output is false.
Note, that in the plot window of a Modelica simulator, the output of this block is usually identically to false, because the output may only be true at an event instant, but not during continuous integration. In order to check that this component is actually working as expected, one should connect its output to, e.g., component ModelicaAdditions.Blocks.Discrete.TriggeredSampler.