modelFlybackConverterDEVS

ModelicaDEVS simulation of the flyback converter.

Information

ModelicaDEVS Flyback Converter

In order to be able to model the flyback converter in ModelicaDEVS or PowerDEVS, we need to map the behaviour of the converter to a block diagram, which then can be reproduced by means of the components from the PowerDEVS/ModelicaDEVS libraries. Block diagrams are obtained by causalising the equations of the system (circuit) according to the Tarjan algorithm as explained in [Cellier05].
Unfortunately in our case, the presence of the switch coupled with the directed input-output data flow intrinsic to DEVS models cause an unsolvable problem if we just attempt to build our block diagram from the common set of equations given in FlybackConverterDymola. It is therefore necessary to split the equations in two sets, one for each switch position (for each operation phase of the converter), thereby eliminating the switching component. The following figure shows the respective electrical circuits for the two switch positions (closed/open).

The following sets of equations describe the two operation phases of the converter:

Switch closed

U₀ = constant
u_L = U₀
u_L = L * di_L/dt
i_C = C * u_R/dt
u_R = R * i_R
i_R = -i_C
i₀ = i_L

Switch open

i_D = i_L
i_D = i_C+ i_R
u_L = L * di_L/dt
i_C = C * u_R/dt
u_R = R * i_R
u_R = -u_L

Now we have to causalise the equations, where causalising means to determine which equation we solve for which variable. To this end, we apply the Tarjan algorithm [Cellier05]: we mark all variables appearing in the equations with labels "solve for" and "known". By convention [Cellier91], known variables are underlined and variables for which a certain equation has to be solved are put into square brackets.
The following rules help a) to find a good starting point for applying the algorithm, and b) to choose the next variable to be marked:

Outputs of integrators are considered to be known. Hence, if we have an equation like u_L= L * di_L/dt, all variables i_L occurring in other equations can be underlined (remember that known variables are marked by underlining them).
An equation that contains only one unknown variable has to be solved for the particular variable that therefore can be put in square brackets.
A variable that occurs in only one equation has to be obtained from that equation, i.e., the equation has to be solved for the particular variable. Thus, the variable can again be put into square brackets.
As soon as a variable has been put into square brackets, all its further occurrences in other equations can be labelled "known" since the value of that variable will be obtained from the equation where it is labelled "solve for".

The causalised version of the two equation sets listed before looks as follows (in order to be able to trace the algorithm, the variables are numbered in the order they were underlined or bracketed):

Switch closed

[U₀] ^(1b) = constant ^(1a)
[u_L] ^{(1d) = U₀ ^(1c)

u_L ^{(1e) = L * [di_L/dt] ^(1f)

i_C ^{(2e) = C * [du_R/dt] ^(2f)

u_R ^{(2a) = R * [i_R] ^(2b)

i_R ^(2c) = -[i_C] ^(2d)

[i₀] ^(1h) = i_L ^(1g)}}}}

Switch open

[i_D] ^(1b) = i_L ^(1a)
i_D ^(1c) = [i_C]^(2d)+ i_R ^(2c)
u_L ^(3c) = L * [di_L/dt] ^(3d)
i_C ^(2e) = C * [du_R/dt] ^(2f)
u_R ^(2a) = R * [i_R] ^(2b)
u_R ^(3a) = -[u_L] ^(3b)

The two sets of causalised equations define exactly the way variables depend on each other, and we are able to build the required block diagram(s). In order to illustrate how to get from a set of equations to a block diagram, the subsequent list depicts the various steps during the synthesis of the block diagram representing the first set of causalised equations.

Although it theoretically does not matter with which block/equation we start, it is recommended to first insert the integrators.

Our first equation we want to represent preferably depends on the integrator variables: i_C= C * du_R/dt

As a next step we include the equations i_R = -i_C and u_R = R * i_R

There are no dependencies anymore, so we insert an integrator again.

u_L= L * di_L/dt

Finally, we represent the equations u_L= U₀ and i₀= i_L, and thereby complete the block diagram of the first equation set.

The following figure shows the two (finished) block diagrams, where the second one has been built according to the same method that has been applied for the first one.
Note that the two resulting diagrams are not completely different from each other but share common parts, which will be helpful as we shall see soon.

The last step towards a complete single block diagram representing the flyback converter, is to merge the two partial diagrams presented above. To this end, recall that initially, we split the original set of equations to eliminate the switch, or, in other terms, to obtain a diagram for each switch position. Hence, while merging the two diagrams, we have to re-insert the switching component. The switch can be said to alternate between the two diagrams: when it is open, the first block diagram is valid, when it is closed, the second one becomes active.
Fortunately, the two diagrams share a similar structure, which eases the merging process a lot: normally we would have to build both of the models and in some way deactivate one of them when the other becomes active. In our case however, we just look for a way how to transform one of the diagrams into the other one. We find that the two critical variables are u_L and i_C since their definition in the first diagram is different from their definition in the second one:

When the switch is closed (first diagram), u_L equals u₀, thus the constant value given by the parameters of the model. The current i_C depends only on i_R instead of a second variable as it is the case for the situation of an open switch.
When the switch is open (second diagram), u_L is equal to -u_R and i_C is determined by both i_D and i_R.

Hence, if we place our switching component in such a way that it switches a) the value for u_L between u₀ and -u_R, and b) the value of i_C between -i_R and i_D-i_R, we obtain a model that fully represents the flyback converter.
Such a model is shown in the subsequent figure. Note that there are still two switches, which however correctly represent the single switch in the original flyback converter, since they flip at the same time and thus could be coupled.

The corresponding ModelicaDEVS model is built according to the model in the figure above, and hence its structure should be clear to a large extent. Only the switching parts may need a brief explanation.

The Square block controls the flipping frequency of the two switches. It generates a signal that oscillates between 1 and 0 (1 = switch open, 0 = switch closed).
The upper switch in the above figure is modelled by a Switch block with the parameter level set to zero. It is important to mention that a level value of 1 would not yield the same results since the Switch connects the first input port to the output port if the second input port is bigger than the level value and the third input port otherwise, namely if the second input port is smaller or equal than the value of level. Hence, the switch would not flip at all.
The Constant block represents the input voltage u₀.
Given that the switch either directs the first or the third input port to its output port, depending on the output of the Square block, this set-up provides the Gain1 block with either the constant value (u₀) or the signal from the Integrator2 block (u_R).
The lower switch is represented by a simple Multiplier block the output of which represents the current i_D. Due to the multiplication of the output of Integrator1 (i_L) by the signal from the Square block (0 or 1), i_D oscillates between 0 (phase 1, switch closed) and the value it is provided by Integrator1 (phase 2, switch open).
This precisely corresponds to the real situation where the current through the diode is zero during phase 1 (diode locked), and non-zero during phase 2.

Output:

The four output variables, Inductor_i_DEVS, Inductor_i, Resistor_u and Resistor_u, give both the original DEVS output and the interpolated version of the current through the inductor and the voltage across the load resistance.

Components

Type	Name	Default	Description
Real	Inductor_i
Real	Resistor_u
Real	Inductor_i_DEVS
Real	Resistor_u_DEVS
ModelicaDEVS.FunctionBlocks.Integrator	Integrator1
ModelicaDEVS.FunctionBlocks.Integrator	Integrator2
ModelicaDEVS.FunctionBlocks.Gain	Gain1
ModelicaDEVS.FunctionBlocks.Gain	Gain2
ModelicaDEVS.FunctionBlocks.Gain	Gain3
ModelicaDEVS.FunctionBlocks.Gain	Gain4
ModelicaDEVS.FunctionBlocks.Add	Add1
ModelicaDEVS.SourceBlocks.Square	Square1
ModelicaDEVS.FunctionBlocks.Switch	Switch1
ModelicaDEVS.SourceBlocks.Constant	Constant1
ModelicaDEVS.FunctionBlocks.Multiplier	Multiplier1
ModelicaDEVS.SinkBlocks.Interpolator	Interpolator1
ModelicaDEVS.SinkBlocks.Interpolator	Interpolator2
ModelicaDEVS.Miscellaneous.worldModel	world