.Modelica_DeviceDrivers.EmbeddedTargets.STM32F4.Types.PLLP

Main PLL devision factor for system clock

Definition

type PLLP = enumeration(DIV_2, DIV_4, DIV_6, DIV_8);

Generated at 2026-01-09T19:13:54Z by OpenModelicaOpenModelica 1.26.0 using GenerateDoc.mos