.Modelica_Synchronous.RealSignals.Sampler.AssignClockVectorized

Information

This block assigns a clock to the Real vector input signal u and provides u as vector output signal y.

Example

The following example shows two discrete counters. In order to execute the counters with a sample period of 20ms an AssignClockVectorized block is used. Due to clock inference all equations within the blocks are deduced to be active at the clock ticks given by the periodicClock block.

	model	simulation result

At every clock tick (that is every 20ms) the output of the unitDelay1 block is incremented by one and that of the unitDelay2 block is incremented by two. The vector size of the input and output is provided by parameter n=2 which is also shown in the icon of block assignClock1.