.Modelica_Synchronous.RealSignals.Sampler

Information

This package contains blocks that mark boundaries of a clocked partition and transform a Real signal from one partition to the next. Especially, the following blocks are provided:
 

Boundary Type Block Name Description
continuous-time → clocked Sample Sample a continuous-time signal.
SampleClocked Sample and associate a clock to the sampled scalar signal.
SampleVectorizedAndClocked Sample an input vector and associate a clock to the sampled vector signal.
SampleWithADeffects Sample with (simulated) Analog-Digital converter effects including noise.
clocked → continuous-time Hold Hold a clocked signal with zero-order hold.
HoldWithDAeffects Hold with (simulated) Digital-Analog converter effects and computational delay.
clocked → clocked SubSample Sub-sample a signal (output clock is slower as input clock).
SuperSample Super-sample a signal (output clock is faster as input clock).
SuperSampleInterpolated Super-sample a signal with linear interpolation (output clock is faster as input clock).
ShiftSample Shift a signal (output clock is delayed with respect to input clock).
BackSample Shift a signal and start the output clock before the input clock with a start value.
within clocked partition AssignClock Assign a clock to a clocked scalar signal.
AssignClockVectorized Assign a clock to a clocked vector signal.

Additionally, package Utilities contains utility blocks that are used as building blocks for user-relevant blocks. Especially, block UpSample can be used in combination with a FIR filter block to model super-sampling with interpolation and filtering.

Contents

NameDescription
 SampleSample the continuous-time, Real input signal and provide it as clocked output signal (clock is inferred)
 SampleClockedSample the continuous-time, Real input signal and provide it as clocked output signal. The clock is provided as input signal
 SampleVectorizedAndClockedSample the continuous-time, Real input signal vector and provide it as clocked output signal vector. The clock is provided as input signal
 SampleWithADeffectsSample with (simulated) Analog-Digital converter effects including noise
 HoldHold the clocked, Real input signal and provide it as continuous-time output signal (zero order hold)
 HoldWithDAeffectsHold with (simulated) Digital-Analog converter effects and computational delay
 SubSampleSub-sample the clocked Real input signal and provide it as clocked output signal
 SuperSampleSuper-sample the clocked Real input signal and provide it as clocked output signal
 SuperSampleInterpolatedSuper-sample the clocked Real input signal and provide it linearly interpolated as clocked output signal (this is also called an Interpolator)
 ShiftSampleShift the clocked Real input signal by a fraction of the last interval and and provide it as clocked output signal
 BackSampleShift the clock of the Real input signal backwards in time (and access the most recent value of the input at this new clock)
 AssignClockAssigns a clock to a clocked Real signal
 AssignClockVectorizedAssigns a clock to a clocked Real signal vector
 UtilitiesUtility components that are usually not directly used

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