modelDutyCycleD
A PWM modulator that implements the given duty cycle,
i.e., 100*d percent of the switching period, the output
signal is high, th remaining 100*(d-1) percent of the
switching period, the output signal is low.
Extends from DutyCycleAb ( An abstract model with a common circuit for all implementations of a duty cycle controller. Derived models must provide additional pins and additional building blocks that handle either the reference voltage or duty cycle directly. ).
Parameters
| Type | Name | Default | Description |
|---|---|---|---|
| SI.Voltage | Vm (from DutyCycleAb) | 2 | Amplitude voltage of the internal sawtooth voltage generator [V] |
| SI.Voltage | Von (from DutyCycleAb) | 2 | Output on-voltage [V] |
| SI.Frequency | fs (from DutyCycleAb) | 100.e+3 | Switching frequency of the modulator [Hz] |
Connectors
| Type | Name | Default | Description |
|---|---|---|---|
| EL.Interfaces.PositivePin | p (from DutyCycleAb) | Positive output pin | |
| EL.Interfaces.NegativePin | n (from DutyCycleAb) | Negative output pin | |
| Modelica.Blocks.Interfaces.RealInput | d | Duty cycle as a dimensionless value between 0 and 1 |