A PWM modulator that implements the given duty cycle,
i.e., 100*d percent of the switching period, the output
signal is high, th remaining 100*(d-1) percent of the
switching period, the output signal is low.
Generated at 2025-10-07T18:21:17Z
by OpenModelicaOpenModelica 1.25.4 using GenerateDoc.mos
.SMPS.PWM.DutyCycleD