modelSVMpwm

Block generating the pwm pulses for SVM

Information

Spot modification:

  Dimension of 'Switch' changed from 3 to 6
  signals for n-gates added.

PWM generation for space vector modulation, as done e.g. by TI's TMSM320P14 DSP.
A duty ratio a=1 indicates a continuously closed upper switch of the first inverter leg. At a duty ratio a=0, the turn-on time during each PWM period is equally distributed to the lower and upper switch and the resulting mean value of the phase voltage u_a0 is zero. At a duty ratio a=-1, the lower switch is continuously closed, etc.

Parameters

TypeNameDefaultDescription
Modelica.SIunits.TimeT_pwm

Connectors

TypeNameDefaultDescription
Modelica.Blocks.Interfaces.BooleanInputtrigger
Modelica.Blocks.Interfaces.RealInput[3]dutyRatio
Modelica.Blocks.Interfaces.BooleanOutput[6]switch

Components

TypeNameDefaultDescription
Modelica.StateGraph.StateGraphRootstateGraphRoot
Modelica.Blocks.Routing.DeMultiplex3DeMultiplex3_1
Modelica.Blocks.Sources.Constantone
Modelica.Blocks.Math.Feedbackt1
Modelica.Blocks.Math.Gainstart_100
Modelica.Blocks.Logical.GreaterEqualGreaterEqual1
Modelica.Blocks.Math.Gainstart_010
Modelica.Blocks.Math.Feedbackt2
Modelica.Blocks.Math.Gainstart_001
Modelica.Blocks.Math.Feedbackt3
Modelica.Blocks.Logical.GreaterEqualGreaterEqual2
Modelica.Blocks.Logical.GreaterEqualGreaterEqual3
Modelica.Blocks.Math.Addstop_100
Modelica.Blocks.Math.Addstop_010
Modelica.Blocks.Math.Addstop_001
Modelica.Blocks.Logical.GreaterEqualGreaterEqual4
Modelica.Blocks.Logical.GreaterEqualGreaterEqual5
Modelica.Blocks.Logical.GreaterEqualGreaterEqual6
Modelica.Blocks.Discrete.TriggeredSampler[3]load_data
Modelica.Blocks.Logical.TimerTimer
Modelica.Blocks.Math.Gaintime_scaling
Modelica.Blocks.Logical.EdgeEdge
Modelica.Blocks.Logical.NotNot
DutyRatioToCycledutyRtoC
Modelica.Blocks.Logical.AndAnd1
Modelica.Blocks.Logical.NotNot1
Modelica.Blocks.Logical.NotNot2
Modelica.Blocks.Logical.AndAnd2
Modelica.Blocks.Logical.NotNot3
Modelica.Blocks.Logical.AndAnd3
Modelica.Blocks.Logical.NotNot4
Modelica.Blocks.Logical.NotNot5
Modelica.Blocks.Logical.NotNot6